Phase-locked loops (PLLs) have been widely used in high-speed communication systems because PLLs efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL, this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency. The prior art has described ways of selecting operating points of voltage and frequency statically, for example, stopping execution while allowing the PLL to frequency lock to a new frequency. This slows system operations and complicates system design.
One of the key circuits in a PLL is a voltage-controlled oscillator (VCO). Circuits in the PLL generate an error voltage that is coupled to the VCO to control the frequency of the VCO output. By frequency dividing the output of the PLL and feeding it back and comparing it to a low frequency crystal-controlled reference clock, a stable high frequency clock may be generated. The VCO in a PLL typically has a range over which the frequency of the VCO may be voltage-controlled. In systems employing frequency scaling, it is desirable to have a voltage-controlled frequency range for normal voltage operation and another voltage-controlled frequency range for low voltage operation without resorting to two VCOs.
VCO circuits employ ring oscillators comprising an odd number M of inverters in a string or sequence from the basic oscillator block. A transition on the input of the ring oscillator emerges at the output after a delay equal to the sum of the delay through the inverters. This is equal to one half the period of the basic oscillator frequency. By coupling a voltage controlled inverting circuit around inverting stages, the basic oscillator frequency may be modified. This allows a common control voltage to vary the basic frequency thus forming a VCO circuit. If larger changes in frequency are desired, then the odd number M of inverters may be varied by selecting which inverter is the output to feedback to the input. This results in a VCO circuit that has a wider range than is possible with a fixed number of M inverters in a ring oscillator. If the VCO basic frequency is to be modified dynamically, then selecting which of the M inverters is the output, requires circuitry to assure that the switching is done without producing glitches which would cause problems when the VCO is used to produce a computer clock. Providing a VCO that has a selectable frequency range and dynamic frequency switching would be useful in producing with a computer clock a wide variation in system performances.
There is, therefore, a need for a wide range VCO circuit that allows dynamic frequency range changing that is glitch free.